Messages in this thread |  | | | Date | Wed, 10 Feb 2010 17:07:13 +0100 | | Subject | Re: [perfmon2] [PATCH] perf_events: AMD event scheduling (v3) | | From | Stephane Eranian <> |
| |
On Wed, Feb 10, 2010 at 4:59 PM, Drongowski, Paul <paul.drongowski@amd.com> wrote: > Good catch! > > Historically, AMD has treated the bit field EventSelect<7:5> > in model specific register MSRC001_00[03:00] Performance Event > Select Register (PERF_CTL[3:0]) like an "event group selector". > Please see the "BIOS and Kernel Developer's Guide for AMD > Family 10h Processors." > > Typically, EventSelect<7:5> == 0x7 selects Northbridge > events. > > Yes, when the event select value was extended to twelve bits, > it placed this field somewhere in the middle of the full > twelve bit value. ;-) > > Please consider AMD Family 10h event 0x1C0 Retired x87 > Floating Point Operations. This is not a Northbridge event. > If the test is greater than or equal to (e.g., 0x1C0 >= 0x0E0), > then this event will be incorrectly identified as a > Northbridge event. (There are other similar examples.) > Good example.
> So, I would recommend testing EventSelect<7:5> == 0x7 > in order to detect AMD Northbridge events. > Ok, so something like the following would do it:
static inline int amd_is_nb_event(struct hw_perf_event *hwc) { return (hwc->config >> 5) & 0x7 == 0x7; }
|  |