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SubjectRe: [PATCH RESEND percpu#for-next] percpu: align percpu readmostly subsection to cacheline
On 12/27/2010 12:43 PM, Sam Ravnborg wrote:
> It would have been better to include cache.h and then use L1_CACHE_BYTES,
> as the value differs for EV4.
> It will work with 64 as this is the bigger of the two.
> It looks like we could do this for almost all archs.
> But then I am not sure if "L1_CACHE_BYTES" is the same as
> a cacheline on the different archs.

For x86, L1 is definitely not the right cache line to use, in terms of
what matters for SMP sharing. And yes, there are x86's with smaller L1
than L2/3 cache line size.


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