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SubjectRe: [PATCH] ata: pata_at91.c bugfix for high master clock
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Dear Sergei,

> > I do not test this driver, but I think it have the same problem, because
> > it have the same algorithm for timings calculation.
>
> I quickly looked thru both drivers and the algorithm seemed different. :-)

I don't think so...

> > If you will see "cycle" value greater then 63, then problem exists.
>
> I thought the problem was with active pulse width, not total cycle time...

The problem was - the same "cycle" variable used to set up NRD_CYCLE
(max value = 127) and NCS_RD_PULSE (max value = 63).
Where NRD_CYCLE, NCS_RD_PULSE names from datasheet for AT91SAM9.
If NCS_RD_PULSE > 63, then overflow occur and pulse is much longer then
required.
For the 132 MHz, driver use NCS_RD_PULSE = 80 at device detection moment
on my board.
Calculated cycle in at91_ide is the same as for pata_at91 driver.

> > Generally, I does not see any reasons to use at91_ide, because ATA
> > drivers subsystem going to replace IDE drivers.
>
> There may be reasons -- like larger thruput in PIO mode (you have to check
> this though -- but generally libata seems very slow in PIO). Anyway, it
> doesn't mean that the bugs in IDE drivers should be ignored, and the
> replacemtn will not happen anytime soon (not all IDE drivers are ported to
> libata yet).

I will send next patch where this driver corrected and tested.

Best regards!
--
Igor Plyatov



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