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    SubjectRe: [PATCH 3/4] perf-events: Add support for supplementary event registers v3
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    On Mon, Nov 22, 2010 at 1:23 PM, Lin Ming <lin@ming.vg> wrote:
    > On Thu, Nov 18, 2010 at 6:47 PM, Andi Kleen <andi@firstfloor.org> wrote:
    >> From: Andi Kleen <ak@linux.intel.com>
    >>
    >> Intel Nehalem/Westmere have a special OFFCORE_RESPONSE event
    >> that can be used to monitor any offcore accesses from a core.
    >> This is a very useful event for various tunings, and it's
    >> also needed to implement the generic LLC-* events correctly.
    >>
    >> Unfortunately this event requires programming a mask in a separate
    >> register. And worse this separate register is per core, not per
    >> CPU thread.
    >
    > This "separate register" is MSR_OFFCORE_RSP_0, right?
    > But from the SDM,  MSR_OFFCORE_RSP_0 is "thread" scope,
    > see SDM 3b, Appendix B.4 MSRS IN THE INTEL® MICROARCHITECTURE CODENAME NEHALEM
    >
    > Or am I missing some obvious thing?
    >
    The manual is wrong on this.

    > Thanks,
    > Lin Ming
    >
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