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    SubjectRe: [PATCH 1/3] perf-events: Add support for supplementary event registers
    On Thu, Nov 11, 2010 at 08:09:14PM +0100, Peter Zijlstra wrote:

    Thanks for the review. I discovered another problem on my own too.

    > > + int percore_used;
    > > + struct intel_percore *per_core;
    >
    > Either per_core != NULL implies percore_used or it should be state
    > inside the struct.

    It does not, I'll clarify.

    > > +#define INTEL_EVENT_EXTRA_REG(event, msr, vm) \
    > > + EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm)
    > > +#define EVENT_EXTRA_END {}
    >
    > Does that imply a zero filled struct?

    Yes.

    > > +++ b/arch/x86/kernel/cpu/perf_event_intel.c
    > > @@ -1,5 +1,14 @@
    > > #ifdef CONFIG_CPU_SUP_INTEL
    > >
    > > +struct intel_percore {
    > > + raw_spinlock_t lock;
    > > + int ref;
    > > + u64 config;
    > > + unsigned extra_reg;
    > > + u64 extra_config;
    > > +};
    > > +static DEFINE_PER_CPU(struct intel_percore, intel_percore);
    >
    > Please dynamically allocate these when needed, just like the AMD
    > north-bridge structure.

    Fully dynamic is difficult because the topology discovery does not
    really handle that nicely.

    I can allocate at boot, but it will not save a lot of memory
    (just one entry per core)

    To be honest I would prefer not to do that change, are you sure
    you want it?

    > I think I like Stephane's suggestion better, frob them into the existing
    > u64 word, since its model specific and we still have 33 empty bits in
    > the control register there's plenty space.

    Ok. I'll see how many changes that needs.

    -Andi

    --
    ak@linux.intel.com -- Speaking for myself only.


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