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    Subject[PATCH 37/43] MN10300: Map userspace atomic op regs as a vmalloc page
    From: Mark Salter <>

    The AM34 processor has an atomic operation that's the equivalent of LL/SC on
    other architectures. However, rather than being done through a pair of
    instructions, it's driven by writing to a pair of memory-mapped CPU control

    One set of these registers (AARU/ADRU/ASRU) is available for use by userspace,
    but for userspace to access them a PTE must be set up to cover the region.
    This is done by dedicating the first vmalloc region page to this purpose,
    setting the permissions on its PTE such that userspace can access the page.

    glibc is hardcoded to expect the registers to be there.

    The way atomic ops are done through these registers is straightforward:

    (1) Write the address of the word you wish to access into AARU. This causes
    the CPU to go and fetch that word and load it into ADRU. The status bits
    are also cleared in ASRU.

    (2) The current data value is read from the ADRU register and modified.

    (3) To alter the data in RAM, the revised data is written back to the ADRU
    register, which causes the CPU to attempt to write it back.

    (4) The ASRU.RW flag (ASRU read watch), ASRU.LW flag (bus lock watch),
    ASRU.IW (interrupt watch) and the ASRU.BW (bus error watch) flags then
    must be checked to confirm that the operation wasn't aborted. If any of
    the watches have been set to true, the operation was aborted.

    Signed-off-by: Mark Salter <>
    Signed-off-by: David Howells <>

    arch/mn10300/include/asm/pgtable.h | 3 +++
    arch/mn10300/mm/init.c | 21 +++++++++++++++++++++
    2 files changed, 24 insertions(+), 0 deletions(-)

    diff --git a/arch/mn10300/include/asm/pgtable.h b/arch/mn10300/include/asm/pgtable.h
    index ba66606..b6e77f5 100644
    --- a/arch/mn10300/include/asm/pgtable.h
    +++ b/arch/mn10300/include/asm/pgtable.h
    @@ -182,6 +182,9 @@ extern pte_t kernel_vmalloc_ptes[(VMALLOC_END - VMALLOC_START) / PAGE_SIZE];

    +#define PAGE_USERIO __pgprot(__PAGE_USERIO)
    * Whilst the MN10300 can do page protection for execute (given separate data
    * and insn TLBs), we are not supporting it at the moment. Write permission,
    diff --git a/arch/mn10300/mm/init.c b/arch/mn10300/mm/init.c
    index 1daf97f..48907cc 100644
    --- a/arch/mn10300/mm/init.c
    +++ b/arch/mn10300/mm/init.c
    @@ -41,6 +41,10 @@ DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);

    unsigned long highstart_pfn, highend_pfn;

    +static struct vm_struct user_iomap_vm;
    * set up paging
    @@ -73,6 +77,23 @@ void __init paging_init(void)
    /* pass the memory from the bootmem allocator to the main allocator */

    + /* The Atomic Operation Unit registers need to be mapped to userspace
    + * for all processes. The following uses vm_area_register_early() to
    + * reserve the first page of the vmalloc area and sets the pte for that
    + * page.
    + *
    + * glibc hardcodes this virtual mapping, so we're pretty much stuck with
    + * it from now on.
    + */
    + user_iomap_vm.flags = VM_USERMAP;
    + user_iomap_vm.size = 1 << PAGE_SHIFT;
    + vm_area_register_early(&user_iomap_vm, PAGE_SIZE);
    + ppte = kernel_vmalloc_ptes;
    + set_pte(ppte, pfn_pte(USER_ATOMIC_OPS_PAGE_ADDR >> PAGE_SHIFT,
    + PAGE_USERIO));

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      Last update: 2010-10-26 05:01    [W:0.063 / U:3.148 seconds]
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