Messages in this thread Patch in this message | | | Date | Fri, 22 Oct 2010 11:34:53 -0700 | From | Greg KH <> | Subject | [26/66] dmaengine: fix interrupt clearing for mv_xor |
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2.6.32-stable review patch. If anyone has any objections, please let us know.
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From: Simon Guinot <sguinot@lacie.com>
commit cc60f8878eab892c03d06b10f389232b9b66bd83 upstream.
When using simultaneously the two DMA channels on a same engine, some transfers are never completed. For example, an endless lock can occur while writing heavily on a RAID5 array (with async-tx offload support enabled).
Note that this issue can also be reproduced by using the DMA test client.
On a same engine, the interrupt cause register is shared between two DMA channels. This patch make sure that the cause bit is only cleared for the requested channel.
Signed-off-by: Simon Guinot <sguinot@lacie.com> Tested-by: Luc Saillard <luc@saillard.org> Acked-by: saeed bishara <saeed.bishara@gmail.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
--- drivers/dma/mv_xor.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/dma/mv_xor.c +++ b/drivers/dma/mv_xor.c @@ -161,7 +161,7 @@ static int mv_is_err_intr(u32 intr_cause static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan) { - u32 val = (1 << (1 + (chan->idx * 16))); + u32 val = ~(1 << (chan->idx * 16)); dev_dbg(chan->device->common.dev, "%s, val 0x%08x\n", __func__, val); __raw_writel(val, XOR_INTR_CAUSE(chan)); }
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