Messages in this thread Patch in this message | | | From | Nicolas Ferre <> | Subject | [PATCH 2/2] AT91: pm: make sure that r0 is 0 when dealing with cache operations | Date | Fri, 22 Oct 2010 19:29:00 +0200 |
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When using CP15 cache operations (c7), we make sure that Rd (r0) is actually 0 as ARM 926 TRM is saying.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> --- arch/arm/mach-at91/pm.c | 1 + arch/arm/mach-at91/pm.h | 2 +- arch/arm/mach-at91/pm_slowclock.S | 1 + 3 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 87a31ba..1d9f204 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -261,6 +261,7 @@ static int at91_pm_enter(suspend_state_t state) * For ARM 926 based chips, this requirement is weaker * as at91sam9 can access a RAM in self-refresh mode. */ + asm("mov r0, #0"); /* clear r0 for CP15 accesses */ asm("b 1f; .align 5; 1:"); asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */ saved_lpr = sdram_selfrefresh_enable(); diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 2c4424b..be081c9 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -21,7 +21,7 @@ static inline u32 sdram_selfrefresh_enable(void) } #define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr) -#define wait_for_interrupt_enable() asm("mcr p15, 0, r0, c7, c0, 4") +#define wait_for_interrupt_enable() asm("mcr p15, 0, r0, c7, c0, 4") /* r0 is 0 here */ #elif defined(CONFIG_ARCH_AT91CAP9) #include <mach/at91cap9_ddrsdr.h> diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S index b6b00a1..f7922a4 100644 --- a/arch/arm/mach-at91/pm_slowclock.S +++ b/arch/arm/mach-at91/pm_slowclock.S @@ -124,6 +124,7 @@ ENTRY(at91_slow_clock) ldr r5, .at91_va_base_ramc1 /* Drain write buffer */ + mov r0, #0 mcr p15, 0, r0, c7, c10, 4 #ifdef CONFIG_ARCH_AT91RM9200 -- 1.7.3
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