[lkml]   [2010]   [Oct]   [18]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
    SubjectRe: [PATCH resend 5/9] MIPS: sync after cacheflush
    On Mon, Oct 18, 2010 at 12:19 PM, Ralf Baechle <> wrote:
    > I'm trying to get a statement from the MIPS architecture guys if the
    > necessity to do anything beyond a cache flush is an architecture violation.

    IMO such a requirement would be unnecessarily strict. Larger flushes
    (e.g. page at a time) tend to benefit from some form of pipelining or
    write gathering. Forcing the processor to flush exactly 32 bytes at a
    time, synchronously, could really slow things down and thrash the
    memory controller.

    I have not been able to find any official statement from MIPS that
    says that CACHE + SYNC should be used, but that seems like the most
    intuitive way to implement things on the hardware side.

     \ /
      Last update: 2010-10-18 21:43    [W:0.020 / U:64.332 seconds]
    ©2003-2016 Jasper Spaans. hosted at Digital OceanAdvertise on this site