Messages in this thread | | | Subject | Re: USB mass storage and ARM cache coherency | From | Catalin Marinas <> | Date | Fri, 29 Jan 2010 16:34:03 +0000 |
| |
On Fri, 2010-01-29 at 16:23 +0000, Ming Lei wrote: > 2010/1/29 Catalin Marinas <catalin.marinas@arm.com>: > > I've been trying for some time to use a rootfs (ext2) on a USB memory > > stick on ARM platforms but without any success. The USB HCD driver is > > ISP1760 which doesn't use DMA. > > > > ARM has a Harvard cache architecture and what I get is incoherency > > between the I and D caches. The CPU I'm using (ARM11MPCore) has PIPT > > caches with D-cache lines allocation on write. > > > > Basically, when user space tries to execute from a new page, it faults > > and the data is requested via the VFS layer, SCSI block device and USB > > mass storage from the ISP1760 driver. The page is then mapped into user > > space and update_mmu_cache() called. > > > > However, since the driver is PIO, the data copied from the USB device > > into RAM gets stuck in the D-cache. On the above page requesting path > > there is no call to flush_dcache_page() to handle D-cache maintenance > > (for DMA drivers, that's handled by the DMA API). > > > > Since the USB mass storage code has the information about the USB driver > > Sorry, I am a little confused that usb mass storage has what information > about DMA or PIO of low level usb transfer?
I was thinking about checking dev->bus->controller->dma_mask which the code (though not the storage one) seems to imply that if the dma_mask is 0, the HCD driver is only capable of PIO.
That would be a more general solution rather than going through each HCD driver since my understanding is that flush_dcache_page() is only needed together with the mass storage support.
-- Catalin
| |