Messages in this thread | | | Subject | RE: [Ptools-perfapi] [perfmon2] [PATCH] perf_events: AMD event scheduling (v1) | From | Peter Zijlstra <> | Date | Fri, 22 Jan 2010 18:42:01 +0100 |
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On Fri, 2010-01-22 at 11:33 -0600, John McCalpin wrote:
> * Think of the system as having four performance monitors per core > *plus* four performance monitors for the "shared" structures on the > chip (L3, crossbar, HyperTransport links, memory controllers).
Would have been nice to have them as a separately addressable pmu instead of shadowing the logical cpu's pmu.
But that's all ancient history of course..
> There is an additional hazard when working with early K8 processors -- > a hardware bug causes the counts of all shared counters to be reset to > zero any time any shared register is programmed. This makes > "protecting" users somewhat more difficult....
Could you qualify early k8 a bit more, it shouldn't be hard to add a quirk for a specific set of cpus to read/reset all counters before writing to the shared pmu.
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