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    Subject[PATCH 09/18] ioat3: enable dca for completion writes
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    Date
    Tag completion writes for direct cache access to reduce the latency of
    checking for descriptor completions.

    Signed-off-by: Dan Williams <dan.j.williams@intel.com>
    ---
    drivers/dma/ioat/dma_v3.c | 3 ++-
    drivers/dma/ioat/registers.h | 1 +
    2 files changed, 3 insertions(+), 1 deletions(-)

    diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c
    index 22af78e..0913d11 100644
    --- a/drivers/dma/ioat/dma_v3.c
    +++ b/drivers/dma/ioat/dma_v3.c
    @@ -167,7 +167,8 @@ static void ioat3_cleanup_tasklet(unsigned long data)
    struct ioat2_dma_chan *ioat = (void *) data;

    ioat3_cleanup(ioat);
    - writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
    + writew(IOAT_CHANCTRL_RUN | IOAT3_CHANCTRL_COMPL_DCA_EN,
    + ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
    }

    static void ioat3_restart_channel(struct ioat2_dma_chan *ioat)
    diff --git a/drivers/dma/ioat/registers.h b/drivers/dma/ioat/registers.h
    index 85d04b8..97d26ea 100644
    --- a/drivers/dma/ioat/registers.h
    +++ b/drivers/dma/ioat/registers.h
    @@ -84,6 +84,7 @@
    /* DMA Channel Registers */
    #define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */
    #define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000
    +#define IOAT3_CHANCTRL_COMPL_DCA_EN 0x0200
    #define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100
    #define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020
    #define IOAT_CHANCTRL_ERR_INT_EN 0x0010


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