Messages in this thread | | | From | "Tan, Wei Chong" <> | Date | Thu, 6 Aug 2009 07:10:00 +0800 | Subject | RE: [GIT PULL] Additional x86 fixes for 2.6.31-rc5 |
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> Sure, we might want the error term to be even smaller, but > in no way does it actually invalidate any of the logic - > the 'tsc' reading is just a guess anyway. Also, I think > that the real issue isn't even an SMI - but the fact that > in the very last iteration of the loop, there's no > serializing instruction _after_ the last 'rdtsc'. So even > in the absense of SMI's, we do have a situation where the > cycle counter was read without proper serialization. >
Hi,
I just recall something which I cannot understand. Earlier when we observed the wrong CPU frequency phenomenon (1666MHz being identified as 1800MHz), we use the same CPU and put them on 2 different boards. On one board, the failure rate is high (about 1 out of every 20). On the other, it almost never fails. We compare the 2 boards and they are quite close to each other with one very prominent difference. The failing board has no PS/2 port and so is using all USB keyboard/mouse while the good board uses PS/2 keyboard/mouse. Thus, we plug in a USB keyboard on the good board and were then able produce the failure on the good board (despite at a lower failure rate, 1 out of every 100). Does this not point to SMI?
Regards, Wei Chong.
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