Messages in this thread | | | Subject | RE: [PATCH v2] powerpc/85xx: Add eSDHC support for MPC8536DS boards | Date | Mon, 31 Aug 2009 15:51:29 +0800 | From | "Hu Mingkai-B21284" <> |
| |
> -----Original Message----- > From: Anton Vorontsov [mailto:avorontsov@ru.mvista.com] > Sent: Friday, August 28, 2009 11:20 PM > To: Hu Mingkai-B21284 > Cc: Kumar Gala; Ben Dooks; linux-kernel@vger.kernel.org; > sdhci-devel@lists.ossman.eu; linuxppc-dev@ozlabs.org; Andrew > Morton; Pierre Ossman; David Vrabel > Subject: Re: [PATCH v2] powerpc/85xx: Add eSDHC support for > MPC8536DS boards > > On Fri, Aug 28, 2009 at 07:02:51PM +0800, Hu Mingkai-B21284 wrote: > > > On Tue, Aug 18, 2009 at 08:24:17PM -0500, Kumar Gala wrote: > > > > > > > > On Aug 18, 2009, at 6:38 PM, Anton Vorontsov wrote: > > > > > > > > >This patch simply adds sdhci node to the device tree. > > > > > > > > > >We specify clock-frequency manually, so that eSDHC will > > > work without > > > > >upgrading U-Boot. Though, that'll only work for default setup > > > > >(1500 > > > > >MHz) on new board revisions. For non-default setups, it's > > > recommended > > > > >to upgrade U-Boot, since it will fixup clock-frequency > > > automatically. > > > > > > > > > >Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> > > > > > > > > out of interest the 85xx eSDHC don't need the sdhci,wp-inverted > > > > property? > > > > > > Yes, eSDHC controllers in MPC85xx report normal state in its > > > registers. > > > > > > > Hi Anton, > > > > The eSDHC controller in different silicon version on > MPC8536 reports > > different WP state in the register PRSSTAT: > > Thanks a million for the heads up! > > Yes, the manual I used ("MPC8536ERM Rev. 0 10/2008") doesn't > mention that, but the newer manual that I just downloaded > ("MPC8536ERM Rev. 1 > 05/2009") does. > > [...] > > For silicon 1.0, the macro > SDHCI_QUIRK_INVERTED_WRITE_PROTECT is also > > defined, so the dirver will report the error WP state in function > > sdhci_get_ro. > > Not any longer. We don't actually define it for any 85xx CPUs. > > I need to think how should we handle all these WP inversions. :-) > > So, we have inversion in BCSR (depending on the BCSR > revision), configurable inversion in CPU via GENCFGR for 1.1 > silicon, and non-configurable non-inverted reporting for 1.0 > silicon... > > Do you know if there are any plans to fix the WP inversion > for MPC8569E-MDS boards, or make something like GENCFGR for > MPC8569 CPUs? > > Thanks, >
Sorry, I also don't know the plan to MPC8569 CPU, but if I get any info, I'll inform you ASAP. :-)
Best regards, Mingkai
> -- > Anton Vorontsov > email: cbouatmailru@gmail.com > irc://irc.freenode.net/bd2 > >
| |