Messages in this thread Patch in this message | | | Date | Thu, 13 Aug 2009 12:49:55 -0700 | From | Greg KH <> | Subject | [patch 20/74] drm/i915: Set SSC frequency for 8xx chips correctly |
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2.6.30-stable review patch. If anyone has any objections, please let us know.
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From: Ma Ling <ling.ma@intel.com>
(cherry picked from commit 6ff4fd05676bc5b5c930bef25901e489f7843660)
All 8xx class chips have the 66/48 split, not just 855.
Signed-off-by: Ma Ling <ling.ma@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> --- drivers/gpu/drm/i915/intel_bios.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-)
--- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -185,10 +185,12 @@ parse_general_features(struct drm_i915_p dev_priv->lvds_use_ssc = general->enable_ssc; if (dev_priv->lvds_use_ssc) { - if (IS_I855(dev_priv->dev)) - dev_priv->lvds_ssc_freq = general->ssc_freq ? 66 : 48; - else - dev_priv->lvds_ssc_freq = general->ssc_freq ? 100 : 96; + if (IS_I85X(dev_priv->dev)) + dev_priv->lvds_ssc_freq = + general->ssc_freq ? 66 : 48; + else + dev_priv->lvds_ssc_freq = + general->ssc_freq ? 100 : 96; } } }
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