Messages in this thread Patch in this message | | | From | Andi Kleen <> | Subject | [PATCH] [8/8] x86: mce: Lower maximum number of banks to architecture limit | Date | Thu, 9 Jul 2009 00:31:45 +0200 (CEST) |
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The Intel x86 architecture right now only supports 32 machine check banks, more would bump into other MSRs.
So lower the max define to 32.
This only affects a few bitmaps, most data structures are dynamically sized anyways.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
--- arch/x86/include/asm/mce.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)
Index: linux/arch/x86/include/asm/mce.h =================================================================== --- linux.orig/arch/x86/include/asm/mce.h +++ linux/arch/x86/include/asm/mce.h @@ -130,10 +130,11 @@ void mce_log(struct mce *m); DECLARE_PER_CPU(struct sys_device, mce_dev); /* - * To support more than 128 would need to escape the predefined - * Linux defined extended banks first. + * Maximum banks number. + * This is the limit of the current register layout on + * Intel CPUs. */ -#define MAX_NR_BANKS (MCE_EXTENDED_BANK - 1) +#define MAX_NR_BANKS 32 #ifdef CONFIG_X86_MCE_INTEL extern int mce_cmci_disabled;
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