Messages in this thread |  | | | Date | Sat, 4 Jul 2009 01:40:23 +0200 | | From | Andi Kleen <> | | Subject | Re: [numbers] perfmon/pfmon overhead of 17%-94% |
On Fri, Jul 03, 2009 at 05:25:32PM -0400, Vince Weaver wrote: > >Vince Weaver <vince@deater.net> writes: > >> > >>as I said in a previous post, on most x86 chips the instructions_retired > >>counter also includes any hardware interrupts that occur during the > >>process runtime. > > > >On the other hand afaik near all chips have interrupt performance counter > >events. > > I guess by "near all" you mean "only AMD"? The AMD event also has some
Intel CPUs typically have HW_INT.RX event. AMD has a similar event.
> well, it's basically at least HZ extra instructions per however many > seconds your benchmark runs, and unfortunately it's non-deterministic > because it depends on keyboard/network/usb/etc interrupts too that may by > chance happen while your program is running. > > For me, it's the determinism that matters. Not overhead, not runtime not
To be honest I don't think you'll ever be full deterministic. Modern computers and operating systems are just too complex with too many (often unpredictable) things going on in the background. In my own experience even simulators (which are much more stable than real hardware) are not fully deterministic. You'll always run into problems.
If you need 100% deterministic use a simple micro controller.
-Andi -- ak@linux.intel.com -- Speaking for myself only.
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