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    Subject[PATCH 11/14] amd64_edac: decode instruction cache MCEs
    Date
    See Fam10h BKDG (31116, rev. 3.28), Table 95.

    Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
    ---
    drivers/edac/amd64_edac.c | 51 +++++++++++++++++++++++++++++++++++++++++++++
    1 files changed, 51 insertions(+), 0 deletions(-)

    diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
    index ee13d59..2a810c1 100644
    --- a/drivers/edac/amd64_edac.c
    +++ b/drivers/edac/amd64_edac.c
    @@ -2296,6 +2296,53 @@ wrong_dc_mce:
    pr_warning("Corrupted DC MCE info?\n");
    }

    +static void amd64_decode_ic_mce(u64 mc1_status)
    +{
    + u32 ec = mc1_status & 0xffff;
    + u32 xec = (mc1_status >> 16) & 0xf;
    +
    + pr_emerg(" Instruction Cache Error");
    +
    + if (xec == 1 && TLB_ERROR(ec))
    + pr_cont(": %s TLB multimatch.\n", LL(ec));
    + else if (xec == 0) {
    + if (TLB_ERROR(ec))
    + pr_cont(": %s TLB Parity error.\n", LL(ec));
    + else if (BUS_ERROR(ec)) {
    + if (boot_cpu_data.x86 == 0xf &&
    + (mc1_status & (1ULL << 58)))
    + pr_cont(" during system linefill.\n");
    + else
    + pr_cont(" during attempted NB data read.\n");
    + } else if (MEM_ERROR(ec)) {
    + u8 ll = ec & 0x3;
    + u8 rrrr = (ec >> 4) & 0xf;
    +
    + if (ll == 0x2)
    + pr_cont(" during a linefill from L2.\n");
    + else if (ll == 0x1) {
    + if (rrrr == 0x5)
    + pr_cont(": Parity error during "
    + "data load.\n");
    + else if (rrrr == 0x7)
    + pr_cont(": Copyback Parity/Victim"
    + " error.\n");
    + else if (rrrr == 0x8)
    + pr_cont(": Tag Snoop error.\n");
    + else
    + goto wrong_ic_mce;
    + }
    + } else
    + goto wrong_ic_mce;
    + } else
    + goto wrong_ic_mce;
    +
    + return;
    +
    +wrong_ic_mce:
    + pr_warning("Corrupted IC MCE info?\n");
    +}
    +
    void amd64_decode_nb_mce(struct mem_ctl_info *mci, struct err_regs *regs,
    int handle_errors, int ecc)
    {
    @@ -2393,6 +2440,10 @@ void decode_mce(struct mce *m)
    amd64_decode_dc_mce(m->status);
    break;

    + case 1:
    + amd64_decode_ic_mce(m->status);
    + break;
    +
    case 4:
    regs.nbsl = (u32) m->status;
    regs.nbsh = (u32)(m->status >> 32);
    --
    1.6.3.3



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