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SubjectRe: [PATCH -tip RESEND] perf_counter x86: fix cache_event_ids table

* Jaswinder Singh Rajput <jaswinder@kernel.org> wrote:

> + [C(L1D, READ, ACCESS)] = 0x0f40, /* L1D_CACHE_LD.MESI */
> + [C(L1D, READ, MISSES)] = 0x0140, /* L1D_CACHE_LD.I_STATE */

Dont you see how weird 'access' versus 'misses' reads?

Also, i like the PowerPC style more:

static int mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] =
{
[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
[C(OP_READ)] = { 0, 0x225 },
[C(OP_WRITE)] = { 0, 0x227 },
[C(OP_PREFETCH)] = { 0, 0 },
},
[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
[C(OP_READ)] = { 0x129, 0x115 },
[C(OP_WRITE)] = { -1, -1 },
[C(OP_PREFETCH)] = { 0x634, 0 },
},

See how readable a two dimensional array is?

If we change the definitions on x86 then i'd suggest a small variant
of this:

[C(L1D)] = { /* { ACCESS MISS } */
[C(READ )] = { 0, 0x225 },
[C(WRITE )] = { 0, 0x227 },
[C(PREFETCH)] = { 0, 0 },
},

Ingo


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