Messages in this thread |  | | | Subject | Re: perf_counter Atom patch | | From | Peter Zijlstra <> | | Date | Tue, 23 Jun 2009 11:10:05 +0200 |
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On Tue, 2009-06-23 at 16:34 +0800, Yong Wang wrote: > > you could simply consider having 0 fixed counters and everything else would work > > as expected. But there is a catch, unfortunately, in that there is erratum AE49 > > which says that there is only one enable bit to control the two generic counters > > on Core Duo/Solo.
Ah, that's similar to P6 like machines. The P6 docs say that to disable a counter you should simply write all zeros (except the EN bit for ctr0) to the control register (IIRC).
I suppose we could do something similar on these errata cores, make x86_pmu_disable_counter() write ARCH_PERFMON_EVENTSEL0_ENABLE instead.
Would that work?
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