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    SubjectRe: IV.5 - Intel Last Branch Record (LBR)
    > 5/ Intel Last Branch Record (LBR)
    > Intel processors since Netburst have a cyclic buffer hosted in
    > registers which can record taken branches. Each taken branch is
    > stored into a pair of LBR registers (source, destination). Up
    > until Nehalem, there was not filtering capabilities for LBR. LBR
    > is not an architected PMU feature.
    > There is no counter associated with LBR. Nehalem has a LBR_SELECT
    > MSR. However there are some constraints on it given it is shared
    > by threads.
    > LBR is only useful when sampling and therefore must be combined
    > with a counter. LBR must also be configured to freeze on PMU
    > interrupt.
    > How is LBR going to be supported?

    If there's interest then one sane way to support it would be to
    expose it as a new sampling format (PERF_SAMPLE_*).

    Regarding the constraints - if we choose to expose the branch-type
    filtering capabilities of Nehalem, then that puts a constraint on
    counter scheduling: two counters with conflicting constraints should
    not be scheduled at once, but should be time-shared via the usual

    The typical use-case would be to have no or compatible LBR filter
    attributes between counters though - so having the conflicts is not
    an issue as long as it works according to the usual model.

     \ /
      Last update: 2009-06-22 14:05    [W:0.042 / U:38.564 seconds]
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