Messages in this thread | | | Date | Sat, 13 Jun 2009 13:03:52 +0200 | From | Ingo Molnar <> | Subject | Re: [PATCH 2/2 -tip] x86: perf_counter update AMD hw caching related event table |
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* Jaswinder Singh Rajput <jaswinder@kernel.org> wrote:
> [PATCH 2/2 -tip] x86: perf_counter update AMD hw caching related event table > > AMD shares same hw caching related event table. > > Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
> - [ C(RESULT_ACCESS) ] = 0, > - [ C(RESULT_MISS) ] = 0, > + [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ > + [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */
How did you get to these numbers and have you tested them? (Such information needs to be in the changelog)
Ingo
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