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    SubjectRe: Broken ARM atomic ops wrt memory barriers (was : [PATCH] Add cmpxchg support for ARMv6+ systems)
    On Wed, May 27, 2009 at 12:02:17PM -0400, Mathieu Desnoyers wrote:
    > * Paul E. McKenney (paulmck@linux.vnet.ibm.com) wrote:
    > > On Wed, May 27, 2009 at 10:52:44AM -0400, Mathieu Desnoyers wrote:
    > > > * Catalin Marinas (catalin.marinas@arm.com) wrote:
    > > > > On Tue, 2009-05-26 at 21:22 -0400, Mathieu Desnoyers wrote:
    > > > > > So, my questions is : is ARMv7 weak memory ordering model as weak as
    > > > > > Alpha ?
    > > > >
    > > > > I'm not familiar with Alpha but ARM allows a weakly ordered memory
    > > > > system (starting with ARMv6), it's up to the processor implementer to
    > > > > decide how weak but within the ARM ARM restrictions (section A3.8.2).
    > > > >
    > > > > I think the main difference with Alpha is that ARM doesn't do
    > > > > speculative writes, only speculative reads. The write cannot become
    > > > > visible to other observers in the same shareability domain before the
    > > > > instruction occurs in program order. But because of the write buffer,
    > > > > there is no guarantee on the order of two writes becoming visible to
    > > > > other observers in the same shareability domain. The reads from normal
    > > > > memory can happen speculatively (with a few restrictions)
    > > > >
    > > > > Summarising from the ARM ARM, there are two terms used:
    > > > >
    > > > > Address dependency - an address dependency exists when the value
    > > > > returned by a read access is used to compute the virtual address
    > > > > of a subsequent read or write access.
    > > > >
    > > > > Control dependency - a control dependency exists when the data
    > > > > value returned by a read access is used to determine the
    > > > > condition code flags, and the values of the flags are used for
    > > > > condition code checking to determine the address of a subsequent
    > > > > read access.
    > > > >
    > > > > The (simplified) memory ordering restrictions of two explicit accesses
    > > > > (where multiple observers are present and in the same shareability
    > > > > domain):
    > > > >
    > > > > * If there is an address dependency then the two memory accesses
    > > > > are observed in program order by any observer
    > > > > * If the value returned by a read access is used as data written
    > > > > by a subsequent write access, then the two memory accesses are
    > > > > observed in program order
    > > > > * It is impossible for an observer of a memory location to observe
    > > > > a write access to that memory location if that location would
    > > > > not be written to in a sequential execution of a program
    > > > >
    > > > > Outside of these restrictions, the processor implementer can do whatever
    > > > > it makes the CPU faster. To ensure the relative ordering between memory
    > > > > accesses (either read or write), the software should have DMB
    > > > > instructions.
    > > >
    > > > Great, so no need to worry about smp_read_barrier_depend then, given
    > > > there is an address dependency.
    > >
    > > No need to worry from a CPU viewpoint, but still need to disable any
    > > value-speculation optimizations that the compiler guys might indulge in.
    > >
    >
    > Yes, that's ACCESS_ONCE() job's, right ? (cast to volatile * and
    > dereference again to hide from compiler)

    Yep!!!

    Thanx, Paul


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