Messages in this thread | | | From | "Michael S. Zick" <> | Subject | Re:[VIA Support] was: [BUG FIX] Make x86_32 uni-processor Atomic ops, Atomic | Date | Wed, 27 May 2009 07:18:08 -0500 |
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On Sun May 24 2009, Harald Welte wrote: > > Once I understand it in full detail, I can talk to the right people inside > CentaurLabs (VIA's CPU division). > > If somebody (optionally) can phrase a precise technical question that I can > directly forward to somebody with low-level x86 knowledge but no Linux background, > it would definitely help speeding up the process. >
What is the PCI Cache Line size in the CX700? In the CN896?
Ref: arch/x86/pci/common.c
As in: /* * Assume PCI cacheline size of 32 bytes for all x86s except K7/K8 * and P4. It's also good for 386/486s (which actually have 16) * as quite a few PCI devices do not support smaller values. */
pci_cache_line_size = 32 >> 2; if (c->x86 >= 6 && c->x86_vendor == X86_VENDOR_AMD) pci_cache_line_size = 64 >> 2; /* K7 & K8 */ else if (c->x86 > 6 && c->x86_vendor == X86_VENDOR_INTEL) pci_cache_line_size = 128 >> 2; /* P4 */
A problem with cache coherency, alignment, or consistency would explain the problems I am seeing - and the differences in the test cases.
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