[lkml]   [2009]   [Apr]   [17]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
    SubjectRe: Scheduler regression: Too frequent timer interrupts(?)
    On Fri, 17 Apr 2009, Peter Zijlstra wrote:

    > > often must occur in parallel on multiple cores. Processing is delayed if
    > > any of the cores encounters a delay due to OS noise.
    > So you have hard deadlines in the order of us? Are these SCHED_FIFO
    > tasks or SCHED_OTHER?

    SCHED_FIFO has the effect of removing all the involuntary context switches
    but it does not effect the other interrutions.

    > Your Xeon is a core2 class machine and should have relatively stable
    > TSC, however its also a dual socket, which I think defeats the
    > stable-ness.

    > What clocksource do you have?
    > cat /sys/devices/system/clocksource/clocksource0/current_clocksource

    cat /sys/devices/system/clocksource/clocksource0/current_clocksource

    > Also, looking over the rest of the scheduler tick code, I can't really
    > see what would be so expensive.

    The expensiveness may be fine if we can limit the number of occurences.
    Maybe the histograms for those releases give more insight.

     \ /
      Last update: 2009-04-17 22:45    [W:0.037 / U:48.440 seconds]
    ©2003-2016 Jasper Spaans. hosted at Digital OceanAdvertise on this site