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    SubjectRe: [PATCH v3 0/6] ATS capability support for Intel IOMMU
    On Fri, Mar 20, 2009 at 07:15:51PM +0800, David Woodhouse wrote:
    > On Fri, 2009-03-20 at 10:47 +0800, Zhao, Yu wrote:
    > > If it's possible, I'd like it go through the PCI tree because the ATS
    > > depends on the SR-IOV. This dependency is not reflected in this v3
    > > series since the SR-IOV is not in-tree and I don't want to break the
    > > build after people apply the ATS on their tree.
    >
    > In what way will it depend on SR-IOV?

    The SR-IOV spec section 3.7.4 says that the Smallest Translation Unit and
    the Invalidate Queue Depth fields in the Virtual Function's ATS capability
    are hard-wired to 0. So we need some special handling when enabling the ATS
    capability for the Virtual Function.

    Table 3-26: ATS Capability Register
    -------------+-----------------------------------------+---------------+--------------
    Bit Location | PF and VF Register Differences From ATS | PF Attributes | VF Attributes
    -------------+-----------------------------------------+---------------+--------------
    | Smallest Translation Unit (STU) | |
    20:16 | Hardwired to 0 for VFs. | ATS | RO
    | PF value applies to all VFs. | |
    -------------+-----------------------------------------+---------------+--------------
    | Invalidate Queue Depth | |
    28:24 | Hardwired to 0 for VFs. | ATS | RO
    | Depth of shared PF input queue. | |
    -------------+-----------------------------------------+---------------+--------------

    > > So Dave, can I get an ack from you and let Jesse pull the IOMMU change
    > > to his tree? Or let this ATS go to 2.6.31?
    >
    > Want to show the latest version of the patches which depend on SR-IOV,
    > and I can ack them?

    Sure, thanks!


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