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    Subject[PATCH] oprofile: don't set counter width from cpuid on core2
    -----BEGIN PGP SIGNED MESSAGE-----
    Hash: SHA1

    resetting the counter width of the performance counters on intel's
    core2, breaks the delivery of NMIs, when running in x86_64 mode.

    this should fix bug #12395:
    http://bugzilla.kernel.org/show_bug.cgi?id=12395

    Signed-off-by: Tim Blechmann <tim@klingt.org>
    - ---
    arch/x86/oprofile/op_model_ppro.c | 8 ++++++++
    1 files changed, 8 insertions(+), 0 deletions(-)

    diff --git a/arch/x86/oprofile/op_model_ppro.c b/arch/x86/oprofile/op_model_ppro.c
    index e9f80c7..ecba9f2 100644
    - --- a/arch/x86/oprofile/op_model_ppro.c
    +++ b/arch/x86/oprofile/op_model_ppro.c
    @@ -78,10 +78,18 @@ static void ppro_setup_ctrs(struct op_msrs const * const msrs)
    if (cpu_has_arch_perfmon) {
    union cpuid10_eax eax;
    eax.full = cpuid_eax(0xa);
    +
    + /* For core2 (family 6, model 15), don't reset the counter width */
    + if (eax.split.version_id == 0 && current_cpu_data.x86 == 6 &&
    + current_cpu_data.x86_model == 15)
    + goto clear_all_counters;
    +
    if (counter_width < eax.split.bit_width)
    counter_width = eax.split.bit_width;
    }

    +clear_all_counters:
    +
    /* clear all counters */
    for (i = 0 ; i < num_counters; ++i) {
    if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
    - --
    1.6.1.2
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