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    Subject[040/151] x86: Add new Intel CPU cache size descriptors
    2.6.32-stable review patch.  If anyone has any objections, please let us know.

    ------------------

    From: Dave Jones <davej@redhat.com>

    commit 85160b92fbd35321104819283c91bfed2b553e3c upstream.

    The latest rev of Intel doc AP-485 details new cache descriptors
    that we don't yet support. 12MB, 18MB and 24MB 24-way assoc L3
    caches.

    Signed-off-by: Dave Jones <davej@redhat.com>
    LKML-Reference: <20091110184924.GA20337@redhat.com>
    Signed-off-by: Ingo Molnar <mingo@elte.hu>
    Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

    ---
    arch/x86/kernel/cpu/intel_cacheinfo.c | 3 +++
    1 file changed, 3 insertions(+)

    --- a/arch/x86/kernel/cpu/intel_cacheinfo.c
    +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
    @@ -102,6 +102,9 @@ static const struct _cache_table __cpuin
    { 0xe2, LVL_3, 2048 }, /* 16-way set assoc, 64 byte line size */
    { 0xe3, LVL_3, 4096 }, /* 16-way set assoc, 64 byte line size */
    { 0xe4, LVL_3, 8192 }, /* 16-way set assoc, 64 byte line size */
    + { 0xea, LVL_3, 12288 }, /* 24-way set assoc, 64 byte line size */
    + { 0xeb, LVL_3, 18432 }, /* 24-way set assoc, 64 byte line size */
    + { 0xec, LVL_3, 24576 }, /* 24-way set assoc, 64 byte line size */
    { 0x00, 0, 0}
    };




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