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    SubjectRe: [PATCH 5/6] hw-breakpoints: Arbitrate access to pmu following registers constraints
    On Mon, Nov 09, 2009 at 07:56:21AM +1100, Benjamin Herrenschmidt wrote:
    > On Thu, 2009-11-05 at 21:58 +1100, Paul Mackerras wrote:
    > > Frederic Weisbecker writes:
    > >
    > > > Allow or refuse to build a counter using the breakpoints pmu following
    > > > given constraints.
    > >
    > > As far as I can see, you assume each CPU has HBP_NUM breakpoint
    > > registers which are all interchangeable and can all be used either for
    > > data breakpoints or instruction breakpoints. Is that accurate?
    > >
    > > If so, we'll need to extend it a bit for Power since we have some CPUs
    > > that have one data breakpoint register and one instruction breakpoint
    > > register. In general on powerpc the instruction and data breakpoint
    > > facilities are separate, i.e. we have no registers that can be used
    > > for either.
    > Additionally, we have more fancy facilities that I don't see exposed at
    > all through this interface (we are building an ad-hoc ptrace based
    > interface today so that gdb can make use of them) and we have one guy
    > with crazy constraints that we don't know yet how to deal with:
    > Among others features:
    > - Pairing of two data or instruction breakpoints to create a ranges
    > breakpoint
    > - Data value compare option
    > - Instruction value compare option

    Yeah. The current generic interface is a draft. I'll try to write
    something generic enough to fit in every archs needs.
    This is needed before we expose its perf interface to userpace

    > And now the crazy constraints:
    > - On one embedded core at least we have a case where the core has 4
    > threads, but the data (4) and instruction (2) breakpoint registers are
    > shared. The 'enable' bits are split so a given data breakpoint can be
    > enabled only on some HW threads but that's about it.
    > I'm not sure if there's a realistic way to handle the later constraint
    > though other than just not allowing use of the HW breakpoint function on
    > those cores at all.
    > Ben.

    Yeah this latter one is tricky. Not sure how to handle it either.
    How are these hw-threads considered by the kernel core? As different

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