Messages in this thread | | | Date | Thu, 8 Oct 2009 22:28:29 +0200 | Subject | Re: [PATCH 2/2] perf_events: add event constraints support for Intel processors | From | stephane eranian <> |
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On Thu, Oct 8, 2009 at 10:08 PM, Ingo Molnar <mingo@elte.hu> wrote: > > * David Miller <davem@davemloft.net> wrote: > >> From: stephane eranian <eranian@googlemail.com> >> Date: Wed, 7 Oct 2009 14:31:58 +0200 >> >> > What PPC does is probably the only way to do this given the interface between >> > generic and machine-specific code. The one advantage I see is that it works >> > inside an event group but also across event groups because that code does not >> > look at group boundary, it only looks at the events and the number of available >> > registers. The downside is that you duplicate state. >> > >> > Did I get this right, Paul? >> >> That's basically how his code works, yes. I intend on duplicating it >> to some extent on sparc64 since I'm operating in a similar problem >> space. >> >> So if at least some of this engine went to a generic place, there'd be >> at least a 3rd user :-) > > Yeah, i'd definitely suggest to generalize this. We've missed updating > PowerPC lowlevel details a couple of times in perf core updates, just > because it's in a non-obvious place. Even if it's used by just a single > arch, generic code is much more visible. >
It is not clear how you can do this without creating a monster. As I said the constraints can be far more difficult than just event X => allowed_counter_bitmask. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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