Messages in this thread |  | | | Date | Mon, 26 Oct 2009 16:48:46 +0900 | | From | Kenji Kaneshige <> | | Subject | Re: [PATCH] pci: pciehp update the slot bridge res to get big range for pcie devices |
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Yinghai Lu wrote: > Kenji Kaneshige wrote: >> Yinghai Lu wrote: >>> move out bus_size_bridges and assign resources out of pciehp_add_bridge() >>> and at last do them all together one time including slot bridge, to >>> avoid to call >>> assign resources several times, when there are several bridges under >>> the slot bridge. >>> >>> need to introduce pci_bridge_assign_resources there. >>> >>> handle the case the first bridge that doesn't get pre-allocated big >>> enough res from FW. >>> for example pcie devices need 256M, but the bridge only get >>> preallocated 2M... >>> >> Though I have not looked at the patch deeply yet (sorry), I have >> some questions and concerns about this change. Please correct me >> if my understanding is not correct. >> >> - Your patch doesn't seems to have the code to free resources. >> If we need to expand the resource range, don't we need to free >> preallocated resource before allocating the new one? > > that is done with pci_bus_size_bridges ==> pbus_size_io/pbus_size_mem ==> find_free_bus_resource ==> release_resource. >
I didn't noticed that find_free_bus_resource() was changed to call release_resource() recently...
By the way, does this (release_resource() by find_bus_resource()) change the resource assignment by BIOS also for bridges other than the ports with hotplug slot (switch upstreamport, for example)?
>> - Your patch seems to update BARs for bridge itself. I think it >> would break the bridge's driver (port service driver) that if >> it controls the device's capability by using IO/Mem, though I >> don't know if such driver or capabilities exists now. > > port service driver will be AER and pciehotplug. > it seems those driver are not use those BAR... > those BAR are supposed for the devices under the pcie bridge. >
I understand that there are only two port service drivers (AER and PCIe hotplug) and both doesn't use BAR. But I still have a concern that changing bridge's BARs might cause problems in the future. In my understanding, what you need is expanding IO/Mem base and limit of root or switch downstream ports. If so, I think we should only touch IO/Mem base/limit, and should not touch bridge's BARs.
Thanks, Kenji Kaneshige
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