Messages in this thread | | | Date | Mon, 05 Jan 2009 18:29:56 -0700 | From | Dan Williams <> | Subject | Re: [PATCH] dmatest: flush and invalidate destination buffer before DMA |
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Atsushi Nemoto wrote: > On Mon, 5 Jan 2009 11:31:57 -0700, "Dan Williams" <dan.j.williams@intel.com> wrote: > Yes, MIPS and ARM do different thing on partial cache line. But I > suppose this belongs to "implementation dependent" area of DMA API so > users of the API should not depend on it. (Well, maybe I'm biased to > MIPS ;-)) > > In general, drivers must not put normal data and DMA buffer on same > cacheline anyway to avoid unexpected writeback and data loss. So this > ambiguity is not a problem. IMHO writeback of the partial line for > DMA_FROM_DEVICE just _hides_ abusing of the DMA API and potential data > loss.
Hmm... one implementation does the right thing in all cases. The other silently allows data corruption unless each callsite that accidentally or purposely passes cacheline-unaligned buffers adds extra maintenance code. Which implementation are you biased towards now? :-).
-- Dan
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