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    Subject[PATCH C 02/13] OMAP3 clock: DPLL{1,2}_FCLK clksel can divide by 4
    Date
    OMAP34xx ES2 TRM Delta G to H states that the divider for DPLL1_FCLK and
    DPLL2_FCLK can divide by 4 in addition to dividing by 1 and 2. Encode this
    into the OMAP3 clock framework.

    linux-omap source commit is 050684c18f2ea0b08fdd5233a0cd3c7f96e00a0e.

    Signed-off-by: Paul Walmsley <paul@pwsan.com>
    Signed-off-by: Tony Lindgren <tony@atomide.com>
    ---
    arch/arm/mach-omap2/clock34xx.h | 20 ++++++++++++++++----
    1 files changed, 16 insertions(+), 4 deletions(-)

    diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
    index 781da12..9d123c6 100644
    --- a/arch/arm/mach-omap2/clock34xx.h
    +++ b/arch/arm/mach-omap2/clock34xx.h
    @@ -1102,8 +1102,15 @@ static struct clk corex2_fck = {

    /* DPLL power domain clock controls */

    -static const struct clksel div2_core_clksel[] = {
    - { .parent = &core_ck, .rates = div2_rates },
    +static const struct clksel_rate div4_rates[] = {
    + { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
    + { .div = 2, .val = 2, .flags = RATE_IN_343X },
    + { .div = 4, .val = 4, .flags = RATE_IN_343X },
    + { .div = 0 }
    +};
    +
    +static const struct clksel div4_core_clksel[] = {
    + { .parent = &core_ck, .rates = div4_rates },
    { .parent = NULL }
    };

    @@ -1113,7 +1120,7 @@ static struct clk dpll1_fck = {
    .init = &omap2_init_clksel_parent,
    .clksel_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
    .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
    - .clksel = div2_core_clksel,
    + .clksel = div4_core_clksel,
    .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
    PARENT_CONTROLS_CLOCK,
    .clkdm = { .name = "cm_clkdm" },
    @@ -1191,7 +1198,7 @@ static struct clk dpll2_fck = {
    .init = &omap2_init_clksel_parent,
    .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
    .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
    - .clksel = div2_core_clksel,
    + .clksel = div4_core_clksel,
    .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
    PARENT_CONTROLS_CLOCK,
    .clkdm = { .name = "cm_clkdm" },
    @@ -1228,6 +1235,11 @@ static struct clk iva2_ck = {

    /* Common interface clocks */

    +static const struct clksel div2_core_clksel[] = {
    + { .parent = &core_ck, .rates = div2_rates },
    + { .parent = NULL }
    +};
    +
    static struct clk l3_ick = {
    .name = "l3_ick",
    .parent = &core_ck,



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