Messages in this thread Patch in this message | | | Date | Thu, 22 Jan 2009 09:28:01 +0100 | From | Ingo Molnar <> | Subject | Re: Fail to early boot with v2.6.27-rc2 to at least v2.6.29-rc2 due to dc1e35c |
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* Avuton Olrich <avuton@gmail.com> wrote:
> On Wed, Jan 21, 2009 at 4:38 PM, H. Peter Anvin <hpa@zytor.com> wrote: > > Avuton Olrich wrote: > >> > >> Hello, > >> > >> My computer fails to make it past 'Unpacking kernel' with anything > >> later than dc1e35, to at least v2.6.29-rc2 due to dc1e35c, at least so > >> git bisect told me. While writing this bug I discovered I was using > >> gcc-4.1.1 when I thought I was using gcc-4.3.2; I upgraded, recompiled > >> 2.6.28.1 and same results so I assume the same results would come from > >> me doing the 4 hour bisect again. > >> > > > > Hi Avuton, > > > > Could you apply these two patches and verify that they work, even with the > > BIOS CPUID level limit enabled? > > Worked perfect, again thanks!
Thanks Avuton - i've updated the commit with your Tested-by tag, see the final commit below.
Ingo
---------------------> From 066941bd4eeb159307a5d7d795100d0887c00442 Mon Sep 17 00:00:00 2001 From: H. Peter Anvin <hpa@linux.intel.com> Date: Wed, 21 Jan 2009 15:04:32 -0800 Subject: [PATCH] x86: unmask CPUID levels on Intel CPUs
Impact: Fixes crashes with misconfigured BIOSes on XSAVE hardware
Avuton Olrich reported early boot crashes with v2.6.28 and bisected it down to dc1e35c6e95e8923cf1d3510438b63c600fee1e2 ("x86, xsave: enable xsave/xrstor on cpus with xsave support").
If the CPUID limit bit in MSR_IA32_MISC_ENABLE is set, clear it to make all CPUID information available. This is required for some features to work, in particular XSAVE.
Reported-and-bisected-by: Avuton Olrich <avuton@gmail.com> Tested-by: Avuton Olrich <avuton@gmail.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> --- arch/x86/kernel/cpu/intel.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 8ea6929..43c1dcf 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -29,6 +29,16 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) { + u64 misc_enable; + + /* Unmask CPUID levels if masked */ + if (!rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_enable) && + (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID)) { + misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID; + wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable); + c->cpuid_level = cpuid_eax(0); + } + if ((c->x86 == 0xf && c->x86_model >= 0x03) || (c->x86 == 0x6 && c->x86_model >= 0x0e)) set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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