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SubjectRe: 2.6.28-rc9: oprofile regression
On Thu, 15 Jan 2009, Tim Blechmann wrote:
> On Thu, 2009-01-15 at 09:46 +0100, Thomas Gleixner wrote:
> > Tim,
> >
> > On Wed, 14 Jan 2009, Tim Blechmann wrote:
> > > this code (line 81/82), changes counter_width from 32 to 40.
> > >
> > > if (counter_width < eax.split.bit_width)
> > > counter_width = eax.split.bit_width;
> > >
> > > however when removing these lines, and thus keeping the value 32 for
> > > counter_width, doesn't change the behavior, only one NMI per cpu.
> >
> > It would only help, when the reported bit_width would be bogus. We
> > know that you get at least one NMI, so lets look at the results we get
> > there.
>
> it seems, that ppro_check_ctrs is never called:
> [ 982.238639] oprofile: using NMI interrupt.
>
> hth, tim

Hmm, that confuses the hell out of me. Can you try the patch below,
which restores the original code of writing the counter registers ?

Thanks,

tglx
---
Subject: x86-oprofile-debug2.patch
From: Thomas Gleixner <tglx@linutronix.de>
Date: Thu, 15 Jan 2009 21:25:55 +0100
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/oprofile/op_model_ppro.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Index: linux-2.6/arch/x86/oprofile/op_model_ppro.c
===================================================================
--- linux-2.6.orig/arch/x86/oprofile/op_model_ppro.c
+++ linux-2.6/arch/x86/oprofile/op_model_ppro.c
@@ -101,9 +101,9 @@ static void ppro_setup_ctrs(struct op_ms
/* enable active counters */
for (i = 0; i < num_counters; ++i) {
if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
- reset_value[i] = counter_config[i].count;
+ reset_value[i] = (1ULL << 32) - counter_config[i].count;

- wrmsrl(msrs->counters[i].addr, -reset_value[i]);
+ wrmsr(msrs->counters[i].addr, (u32) reset_value[i], 0);

CTRL_READ(low, high, msrs, i);
CTRL_CLEAR(low);
@@ -132,7 +132,7 @@ static int ppro_check_ctrs(struct pt_reg
rdmsrl(msrs->counters[i].addr, val);
if (CTR_OVERFLOWED(val)) {
oprofile_add_sample(regs, i);
- wrmsrl(msrs->counters[i].addr, -reset_value[i]);
+ wrmsr(msrs->counters[i].addr, (u32) reset_value[i], 0);
}
}


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