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    Subject[PATCH 09/16] x86: cpu common merge display_cacheinfo
    Date
    Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com>
    ---
    arch/x86/kernel/cpu/common.c | 8 ++++++++
    arch/x86/kernel/cpu/common_64.c | 17 +++++++++++++++++
    2 files changed, 25 insertions(+), 0 deletions(-)

    diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
    index 2c4bfa2..f919120 100644
    --- a/arch/x86/kernel/cpu/common.c
    +++ b/arch/x86/kernel/cpu/common.c
    @@ -285,6 +285,10 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
    printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
    edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
    c->x86_cache_size = (ecx>>24) + (edx>>24);
    +#ifdef CONFIG_X86_64
    + /* On K8 L1 TLB is inclusive, so don't count it */
    + c->x86_tlbsize = 0;
    +#endif
    }

    if (n < 0x80000006) /* Some chips just has a large L1. */
    @@ -293,6 +297,9 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
    cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
    l2size = ecx >> 16;

    +#ifdef CONFIG_X86_64
    + c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
    +#else
    /* do processor-specific cache resizing */
    if (this_cpu->c_size_cache)
    l2size = this_cpu->c_size_cache(c, l2size);
    @@ -303,6 +310,7 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)

    if (l2size == 0)
    return; /* Again, no L2 cache is possible */
    +#endif

    c->x86_cache_size = l2size;

    diff --git a/arch/x86/kernel/cpu/common_64.c b/arch/x86/kernel/cpu/common_64.c
    index 2fda109..f7a2d52 100644
    --- a/arch/x86/kernel/cpu/common_64.c
    +++ b/arch/x86/kernel/cpu/common_64.c
    @@ -285,8 +285,10 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
    printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
    edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
    c->x86_cache_size = (ecx>>24) + (edx>>24);
    +#ifdef CONFIG_X86_64
    /* On K8 L1 TLB is inclusive, so don't count it */
    c->x86_tlbsize = 0;
    +#endif
    }

    if (n < 0x80000006) /* Some chips just has a large L1. */
    @@ -294,7 +296,22 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)

    cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
    l2size = ecx >> 16;
    +
    +#ifdef CONFIG_X86_64
    c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
    +#else
    +
    + /* do processor-specific cache resizing */
    + if (this_cpu->c_size_cache)
    + l2size = this_cpu->c_size_cache(c, l2size);
    +
    + /* Allow user to override all this if necessary. */
    + if (cachesize_override != -1)
    + l2size = cachesize_override;
    +
    + if (l2size == 0)
    + return; /* Again, no L2 cache is possible */
    +#endif

    c->x86_cache_size = l2size;

    --
    1.5.4.5


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