Messages in this thread |  | | | Date | Sun, 21 Sep 2008 08:27:50 +0300 | | From | Muli Ben-Yehuda <> | | Subject | Re: [PATCH 03/23] AMD IOMMU: implement lazy IO/TLB flushing |
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On Fri, Sep 19, 2008 at 07:43:39PM +0200, Joerg Roedel wrote: > Hi All, > > FUJITA mentioned that I forgot to discuss this patch with you guys, the > implementers and maintainers for Intel VT-d and Calgary IOMMU drivers. I > would like to hear your opinion on that patch. He is right with that. > The patch is already in tip/iommu but can easily be reverted if there > are fundamental objections. > The patch basically moves the iommu=fullflush and iommu=nofullflush > option from the GART code to pci-dma.c. So we can use these parameters > in other IOMMU implementations too. Since Intel VT-d is implementing > also lazy IO/TLB flushing it would benefit from this generic parameter > too. I am not so sure about Calgary, but we have other parameters for > iommu= which doesn't affect all hardware IOMMUs.
Calgary can't use fullflush, but in general the more unified our IOMMU options, the better for the users. It's a pain to have to remember which option applies to which IOMMU implementation.
Cheers, Muli -- Workshop on I/O Virtualization (WIOV '08) Co-located with OSDI '08, Dec 2008, San Diego, CA http://www.usenix.org/wiov08
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