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    Subject[patch 1/2] x2apic: fix reserved APIC register accesses in print_local_APIC()
    From: Yinghai Lu <yhlu.kernel@gmail.com>
    Subject: x2apic: fix reserved APIC register accesses in print_local_APIC()

    APIC_ARBPRI is a reserved register for XAPIC and beyond.
    APIC_RRR is a reserved register for integrated APIC's.
    APIC_EOI is a write only register.
    APIC_DFR is reserved in x2apic mode.

    Access to these registers in x2apic will result in #GP fault. Fix these
    apic register accesses.

    Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com>
    Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
    ---

    Index: tip/arch/x86/kernel/io_apic.c
    ===================================================================
    --- tip.orig/arch/x86/kernel/io_apic.c 2008-09-02 16:04:04.000000000 -0700
    +++ tip/arch/x86/kernel/io_apic.c 2008-09-02 16:17:13.000000000 -0700
    @@ -1751,21 +1751,24 @@
    printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);

    if (APIC_INTEGRATED(ver)) { /* !82489DX */
    - v = apic_read(APIC_ARBPRI);
    - printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
    - v & APIC_ARBPRI_MASK);
    + if (!APIC_XAPIC(ver)) {
    + v = apic_read(APIC_ARBPRI);
    + printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
    + v & APIC_ARBPRI_MASK);
    + }
    v = apic_read(APIC_PROCPRI);
    printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
    + } else {
    + v = apic_read(APIC_RRR);
    + printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
    }

    - v = apic_read(APIC_EOI);
    - printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
    - v = apic_read(APIC_RRR);
    - printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
    v = apic_read(APIC_LDR);
    printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
    - v = apic_read(APIC_DFR);
    - printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
    + if (!x2apic_enabled()) {
    + v = apic_read(APIC_DFR);
    + printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
    + }
    v = apic_read(APIC_SPIV);
    printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);

    Index: tip/include/asm-x86/apic.h
    ===================================================================
    --- tip.orig/include/asm-x86/apic.h 2008-09-02 16:04:04.000000000 -0700
    +++ tip/include/asm-x86/apic.h 2008-09-02 16:15:42.000000000 -0700
    @@ -98,6 +98,20 @@
    extern void enable_x2apic(void);
    extern void enable_IR_x2apic(void);
    extern void x2apic_icr_write(u32 low, u32 id);
    +static inline int x2apic_enabled(void)
    +{
    + int msr, msr2;
    +
    + if (!cpu_has_x2apic)
    + return 0;
    +
    + rdmsr(MSR_IA32_APICBASE, msr, msr2);
    + if (msr & X2APIC_ENABLE)
    + return 1;
    + return 0;
    +}
    +#else
    +#define x2apic_enabled() 0
    #endif

    struct apic_ops {
    --



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