Messages in this thread | | | Date | Tue, 2 Sep 2008 23:13:22 +0200 (CEST) | From | Thomas Gleixner <> | Subject | Re: Regression in 2.6.27 caused by commit bfc0f59 |
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On Tue, 2 Sep 2008, Linus Torvalds wrote: > > You're definitely right that this could easily be the _real_ problem. > Especially as your TSC min value of 2160 is (a) pretty close to the > expected time of a microsecond and (b) so stable that I actually do not > believe that the PIT itself is at all emulated or the problem.
On that box, the PIT is probably real hardware or a damned good emulation. When you look at the 10 loop values you see that it does 50% perfectly fine calibration loops. The others are just SMI interruptions caused by random unknown crap in the BIOS.
> Btw - as to caring about the average value: that's pointless. If you only > look at the average time the PIT read takes place, then it is going to > approximate that "pit_count" thing in the end that I already did. > > Why? Because the average value should essentially end up being "(end_tsc - > start_tsc) / pit_count". And if you just compare that to "min_tsc", then > that should always be about a microsecond (on normal machines where the > PIT is essentially on the old emulated internal "ISA" bus on the > southbridge). So you end up with what I already posted, and you already > dismissed. > > So average TSC is not any more interesting than "pit_count".
Yeah, you're right. Math is hard :)
Thanks,
tglx
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