Messages in this thread | | | Date | Mon, 04 Aug 2008 15:48:17 -0600 | From | Robert Hancock <> | Subject | Re: Kernel Summit request for Discussion of future of ATA (libata) and IDE |
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Alan Cox wrote: >> You mentioned in the thread for Willy's patch that "some >> controllers have quirky rules for 32bit xfers" - any details anywhere? > > There are two main ones > > - Some controllers only support 32bit I/O for a multiple of 32bit values > [sometimes 'unless the fifo is disabled']. I'd have to go back over the > docs but I think the AMD may be one of those
The AMD-766 doc I have says that when the Secondary Posted Write Buffer or Primary Posted Write Buffer are enabled, only 32-bit writes are allowed to the data port. It doesn't say anything about a restriction with the read prefetch buffer though.
I guess it depends if any other controllers could potentially have this restriction. I suspect non-multiple-of-32-bit transfers are rare enough we could just fall back to 16-bit IO always for them, but maybe not.
> - Some controllers (VLB generally) require a magic sequence before the > transfer. You'll see that in the pata_legacy bits. > > Alan >
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