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    SubjectRe: [PATCH 2/2] Add support for > 2GiB MTD devices
    On 27.08.2008 20:51, Jamie Lokier wrote:
    > wrote:
    >> I'm still reluctant to change size to a 64-bit value. There's a vague
    >> recolection of early conversations on the list that there would be little
    >> acceptance for that. And that probably has to do with the ongoing
    >> conversation about ABI changes. What I could do to eliminate the
    >> multiplication is introduce the same concept that the NAND layer uses,
    >> shift values. After all, erasesize should always be a power of 2, making
    >> that a power of 2 multiplication which can be done via shifts. By
    >> changing erasesize to erasesize_shift, I'd get something like this:
    >> return a->num_eraseblocks == 0 ? a->size : a->num_eraseblocks <<
    >> a->erasesize_shift
    >> How would that suit you?
    > Are you sure it's always going to be a power of 2?
    > What if someone targets a board with 3 chips wired to shared address
    > and parallel data buses?
    > Or if someone makes a weird chip? Or if you can format it in
    > different ways according to desired ECC level (like you can with CDs)?

    IIRC I saw a datasheet for such a chip (selectable erasesize with
    non-power-of-2 default) some weeks ago and it had entered production a
    few months ago. The erasesize was alwas a multiple of 16, though. Sorry
    for not remembering more details.



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