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Subject[patch]pageattr: cache flush before tlb flush
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clflush uses a virtual address but cache line is physical indexed in
x86. In my understanding, clflush will do some pagetable walk, so doing
cache flush first should reduce some pagetable walk.

Signed-off-by: Shaohua Li <shaohua.li@intel.com>

diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index f5f5154..d8b24df 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -168,10 +168,8 @@ static void cpa_flush_range(unsigned long start, int numpages, int cache)
BUG_ON(irqs_disabled());
WARN_ON(PAGE_ALIGN(start) != start);

- on_each_cpu(__cpa_flush_range, NULL, 1);
-
if (!cache)
- return;
+ goto tlb_flush;

/*
* We only need to flush on one CPU,
@@ -188,6 +186,9 @@ static void cpa_flush_range(unsigned long start, int numpages, int cache)
if (pte && (pte_val(*pte) & _PAGE_PRESENT))
clflush_cache_range((void *) addr, PAGE_SIZE);
}
+
+tlb_flush:
+ on_each_cpu(__cpa_flush_range, NULL, 1);
}

/*



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