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Subject[PATCH] x86: cacheline_align tss_struct
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The manual padding to align on cacheline size only worked in 32 bit
In 64 bit the structure was not aligned and contained wasted space.

use the compiler ____cachline_aligned to save space & properly align
this structure.

x86_64_default size goes from 9136 -> 8960
x86_64_AMD size goes from 9136 -> 8896


Signed-off-by: Richard Kennedy <richard@rsk.demon.co.uk>
---

Hi Ingo
here's the patch.
built & running on 2.6.26-rc8.

Richard



diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h
index 5591052..4ab2ede 100644
--- a/include/asm-x86/processor.h
+++ b/include/asm-x86/processor.h
@@ -263,15 +263,11 @@ struct tss_struct {
struct thread_struct *io_bitmap_owner;

/*
- * Pad the TSS to be cacheline-aligned (size is 0x100):
- */
- unsigned long __cacheline_filler[35];
- /*
* .. and then another 0x100 bytes for the emergency kernel stack:
*/
unsigned long stack[64];

-} __attribute__((packed));
+} ____cacheline_aligned;

DECLARE_PER_CPU(struct tss_struct, init_tss);




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