Messages in this thread | | | Date | Fri, 1 Aug 2008 00:12:47 +0200 | From | Andi Kleen <> | Subject | Re: [PATCH 2/2] x86: implement multiple queues for smp function call IPIs |
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> Before going into all the fine details an trying our luck in tip/master > QA, i'm a bit worried about hw compatibility in general though. APICs > have been flaky since the beginnings of times. We had erratas in the > area of local timer IRQs(IPIs) overlapping with IPIs, etc. - so i'd not > bet the farm on all APICs being able to handle a _lot_ more overlapped > inter-CPU IPIs than we do currently. (which basically was just three of > them until now, and now four with the new SMP cross-call IPIs)
At least on 64bit systems this configuration has been already tested for years with the 8 vector TLB flush. I am not aware of any problems caused by it. Using them on them should be fine.
So your cautious approach would only be potentially useful on older 32bit only systems.
-Andi
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