Messages in this thread | | | Date | Sun, 20 Jul 2008 10:38:55 +0400 | From | Cyrill Gorcunov <> | Subject | Re: [PATCH] x86: warn on apic error |
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[Maciej W. Rozycki - Sun, Jul 20, 2008 at 12:08:23AM +0100] | On Sat, 19 Jul 2008, Cyrill Gorcunov wrote: | | > [Maciej W. Rozycki - Fri, Jul 18, 2008 at 08:09:20PM +0100] | > | On Fri, 18 Jul 2008, Cyrill Gorcunov wrote: | > | | > | > iirc, they all were there (though some error codes are specific for | > | > particular processor classes like P4, pentium and other - don't remeber | > | > you could check intel dev manual for this). | > | | > | This is an error in some newer Intel documents -- the set of supported | > | bits is the same for all APICs implementing the ESR register and the error | > | interrupt (the 82489DX is the one to provide neither). | > | | > | Maciej | > | | > | > But Maciej, Intel doesn't claim about absence of bit but | > rather about their 'reserved' state so checking the reserved | > bit could be false alarm if it was being set by some reason. | | As I say -- all later manuals have an error here (not the first and | presumably not the last one), where they state the invalid register error | has been only implemented since the P6. This is not true -- go find the | Pentium manual or experiment with actual hardware to see otherwise. No | new bits have been added since the introduction of the ESR, so there is no | issue with bits to mask out on older silicon. | | Obviously the checksum and accept error bits are valid for APICs using | the dedicated inter-APIC bus only as for the FSB they are irrelevant. | They have to be hardwired to zero for backward compatibility though. | | Maciej |
Thanks a lot, Maciej!
- Cyrill -
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