Messages in this thread | | | Date | Tue, 3 Jun 2008 09:46:46 +0200 | From | Haavard Skinnemoen <> | Subject | Re: MMIO and gcc re-ordering issue |
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Scott Wood <scottwood@freescale.com> wrote: > On Mon, Jun 02, 2008 at 10:11:02AM +0200, Haavard Skinnemoen wrote: > > Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > > On Fri, 30 May 2008, Haavard Skinnemoen wrote: > > > > Maybe we need another interface that does not do byteswapping but > > > > provides stronger ordering guarantees? > > > > > > The byte swapping depends on the device/bus. > > > > Of course. But isn't it reasonable to assume that a device integrated > > on the same silicon as the CPU is connected to a somewhat sane bus > > which doesn't require any byte swapping? > > No, unfortunately. :-(
Ok, I guess I was being naive.
> See the end of drivers/dma/fsldma.h. Likewise with Freescale's PCI host > bridges; for some reason the bus itself being little endian led to the host > bridge control registers also being little endian.
Right. But still, isn't it better to handle it on a case-by-case basis in the drivers? In some cases, it's best to explicitly use a certain byte order, in others it's best to use whatever is native to the CPU.
Haavard
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