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On Sat, 10 May 2008, Jesper Krogh wrote: > Rick Jones wrote: > > > > Into which slot was the Neptune inserted? (sure will be nice to have > > Alex Chiang's pci slot id patch in mainline one of these days :) > > > > Is that slot x4, x8, x16? > > I can find out excactly .. on monday. But shouldn't x4 be enough anyway? > wikipedia says 250MB/s pr. lane. And no slots is less than x4, so I > thought that it didn't matter to me. No you need 8x for 10-GigE. The 250 MB/sec per lane is 2 Gbps per lane so 4x is only 8 Gbps. For a typical PCI-E transaction size of 128 bytes, and PCI-E protocol overhead of 20 to 24 bytes, that takes off about 20%, which leaves you with about 6.5 Gbps of usable bandwidth, which is further reduced somewhat by the required PCI-E ACK and flow control packets that accompany the actual data transaction packets. I am not an expert on PCI-E but I believe this info to be generally correct. -Bill -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ | |||||||||
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