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    SubjectRe: MMIO and gcc re-ordering issue
    On Thu, 2008-05-29 at 10:47 -0400, Jes Sorensen wrote:
    > The only way to guarantee ordering in the above setup, is to either
    > make writel() fully ordered or adding the mmiowb()'s inbetween the two
    > writel's. On Altix you have to go and read from the PCI brige to
    > ensure all writes to it have been flushed, which is also what mmiowb()
    > is doing. If writel() was to guarantee this ordering, it would make
    > every writel() call extremely expensive :-(

    Interesting. I've always been taught by ia64 people that mmiowb() was
    intended to be used solely between writel() and spin_unlock().

    I think in the above case, you really should make writel() ordered.
    Anything else is asking for trouble, for the exact same reasons that I
    made it fully ordered on powerpc at least vs. previous stores. I only
    kept it relaxed vs. subsequent cacheable stores (ie, spin_unlock), for
    which I use the trick mentioned before.

    Yes, this has some cost (can be fairly significant on powerpc too) but
    I think it's a very basic assumption from drivers that consecutive
    writel's, especially issued by the same CPU, will get to the device
    in order.

    If this is a performance problem, then provide relaxed variants and
    use them in selected drivers.


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