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    SubjectRe: MMIO and gcc re-ordering issue
    On Tue, 2008-05-27 at 10:38 -0700, Roland Dreier wrote:
    > > Actually, this specifically should not be. The need for mmiowb on altix
    > > is because it explicitly violates some of the PCI rules that would
    > > otherwise impede performance. The compromise is that readX on altix
    > > contains the needed dma flush but there's a variant operator,
    > > readX_relaxed that doesn't (for drivers that know what they're doing).
    > > The altix critical drivers have all been converted to use the relaxed
    > > form for performance, and the unconverted ones should all operate just
    > > fine (albeit potentially more slowly).
    > Is this a recent change? Because as of October 2007, 76d7cc03
    > ("IB/mthca: Use mmiowb() to avoid firmware commands getting jumbled up")
    > was needed. But this was involving writel() (__raw_writel() actually,
    > looking at the code), not readl(). But writel_relaxed() doesn't exist
    > (and doesn't make sense).

    Um, OK, you've said write twice now ... I was assuming you meant read.
    Even on an x86, writes are posted, so there's no way a spin lock could
    serialise a write without an intervening read to flush the posting
    (that's why only reads have a relaxed version on altix). Or is there
    something else I'm missing?


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