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On Wed, 2008-03-26 at 23:10 +0100, Ingo Molnar wrote: > > PCI bridges at zero is perfectly valid indeed and I'm sure we have > > that around at least for IO space. In fact, I'm surprised you don't > > have that on x86. Typically, things like an HT segment with a P2P > > bridge and behind that bridge an ISA bridge could well have the P2P > > bridge with a resource forwarding 0...0x1000 IO downstream for example > > even on x86 no ? (I'm not -that- familiar with the crazyness of legacy > > ISA on x86 but I've definitely seen such setup on other archs). > > 0..0x1000 physical memory (== bus memory on x86) is reserved to the BIOS > as RAM in essence and that legacy will be with us for at least 100 or > maybe 200 years ;-) I was talking about IO not memory mostly here. MMIO wouldn't be a problem on powerpc as I said because we offset MMIO resources early after probe so that they contain effectively a CPU bus address, and in that case, 0 is definitely not going to happen for PCI devices or busses (even if it may on the bus, but the code we are talking about won't see it). Cheers, Ben. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ | |||||||||
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